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Altera_Forum's avatar
Altera_Forum
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16 years ago

I failed to realize double times frequency by using code!

I want to use code to realize double frequency by using code, However I failed.

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the following is the code.

LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

USE IEEE.STD_LOGIC_ARITH.ALL;

USE IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY DOUBLE_FREQ IS

PORT(CLK: IN STD_LOGIC;

CLK_OUT: OUT STD_LOGIC

);

END ENTITY DOUBLE_FREQ;

ARCHITECTURE ART OF DOUBLE_FREQ IS

SIGNAL TEMP1: STD_LOGIC;

SIGNAL TEMP2: STD_LOGIC;

SIGNAL TEMP3: STD_LOGIC;

SIGNAL TEMP4: STD_LOGIC;

BEGIN

TEMP1 <= NOT CLK;

TEMP2 <= NOT TEMP1;

TEMP3 <= NOT TEMP2;

TEMP4 <= NOT TEMP3;

CLK_OUT <= CLK XOR TEMP4;

END ARCHITECTURE ART;

I used some logic gate delay chains , But I can't realize the function.

can you tell me where is the problem?

thanks!

3 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    16 years ago

    You can never rely on logic cells to move signals by any fixed amount. I can see you are trying to move it 50% out of phase so you get a 2x clock. You cannot do this in an FPGA.

    For a start, the synthesisor is going to remove all of the inverters because temp4 = clk. then once all the inverters are removed, clk_out is the same as clk in. The synthesisor minimises boolean logic equations as the first step.

    not ( not ( not (not clk)))) = clk.

    Phase lock loops are used to do what you want. Look into these in the manual of the FPGA that you are using.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    16 years ago

    It can basically work, but you have to consider the special means to tell the synthesis tool to keep the logic cells. With Quartus it's partly different for CPLD and FPGA. Of course the logic cell delay must be large enough to achieve a minimum pulse width required by the respective device family and I/O standard. With Cyclone, a four logic cells chain is equivalent to about 1 ns delay, probably too short.

    Because the topic of logic cell delay has been widely discussed at Altera Forum, I'm sure you'll easily find the previous references. It's also a topic in the Altera advanced synthesis cookbook.

    P.S.: I remembered from your previous posts, that you are targetting to CPLD, which also answers the question, why a PLL isn't an option. Here's a recent thread that discusses the usage of the keep synthesis attribute and the "Ignores LCELL buffers" global synthesis settings, that must be deactivated for CPLD.

    http://www.alteraforum.com/forum/showthread.php?t=22110