I failed to realize double times frequency by using code!

It can basically work, but you have to consider the special means to tell the synthesis tool to keep the logic cells. With Quartus it's partly different for CPLD and FPGA. Of course the logic cell delay must be large enough to achieve a minimum pulse width required by the respective device family and I/O standard. With Cyclone, a four logic cells chain is equivalent to about 1 ns delay, probably too short.

Because the topic of logic cell delay has been widely discussed at Altera Forum, I'm sure you'll easily find the previous references. It's also a topic in the Altera advanced synthesis cookbook.

P.S.: I remembered from your previous posts, that you are targetting to CPLD, which also answers the question, why a PLL isn't an option. Here's a recent thread that discusses the usage of the keep synthesis attribute and the "Ignores LCELL buffers" global synthesis settings, that must be deactivated for CPLD.

http://www.alteraforum.com/forum/showthread.php?t=22110