I failed to realize double times frequency by using code!

You can never rely on logic cells to move signals by any fixed amount. I can see you are trying to move it 50% out of phase so you get a 2x clock. You cannot do this in an FPGA.

For a start, the synthesisor is going to remove all of the inverters because temp4 = clk. then once all the inverters are removed, clk_out is the same as clk in. The synthesisor minimises boolean logic equations as the first step.

not ( not ( not (not clk)))) = clk.

Phase lock loops are used to do what you want. Look into these in the manual of the FPGA that you are using.