Forum Discussion
zlan01
New Contributor
6 years agoI design a board with max10,and do not design the reset input for max10, how can I generate a internal reset ?
Can I use the locked output of pll to generate a reset signal for my design? And what is the best reset mode for max10 ?using a input reset or generating a reset signal just in FPGA ? For my board,t...
ak6dn
Regular Contributor
6 years agoSorry Intel support person Sree you are misinformed and do not know what you are talking about.
I have been using the construct reg [24:0] pup_count = 25'd0; for YEARS now in the Quartus synthesis tools (at least since 11.0sp1) to assign the default initial powerup configuration of a register.
Using the external reset pin to feed into the async reset of a register is NOT necessary. The above construct works just fine for an initial powerup configuration.
Using the async reset pin is ONLY necessary if you want to perform that function AFTER initial powerup configuration.