Forum Discussion

zlan01's avatar
zlan01
Icon for New Contributor rankNew Contributor
6 years ago

I design a board with max10,and do not design the reset input for max10, how can I generate a internal reset ?

Can I use the locked output of pll to generate a reset signal for my design? And what is the best reset mode for max10 ?using a input reset or generating a reset signal just in FPGA ？ For my board,t...
zlan01's avatar
zlan01
Icon for New Contributor rankNew Contributor
6 years ago

SO, The enginner of intel means that the method giving 25'd0 to pup_count is not reliable ?

And the standard process for altera is to input a reset signal to the FPGA ?right ?

ak6dn's avatar
ak6dn
Icon for Regular Contributor rankRegular Contributor
6 years ago

Honestly I don't know what Intel support person Sree is talking about. Maybe they misunderstand the issue.

I have assigned initial power up values to registers using the mechanism I illustrated for YEARS and it works just fine.

The reason to use an external reset signal input is if you want to reset the device state AFTER powerup configuration.

The value assignment to the register is only good after configuring the device (at powerup or anytime a reconfig is triggered).

If you want to do a device reset at an arbitrary time, and not have to force a device reconfiguration, an external reset signal is good for that.

And as I said I have no idea what Sree was referring to. His/her response is basically WRONG.