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zlan01
New Contributor
New ContributorI design a board with max10,and do not design the reset input for max10, how can I generate a internal reset ?
Can I use the locked output of pll to generate a reset signal for my design? And what is the best reset mode for max10 ?using a input reset or generating a reset signal just in FPGA ？ For my board,t...
ak6dn
Regular Contributor
Regular ContributorSREE,
This assignment statement in the above Verilog:
reg [24:0] pup_count = 25'd0;
sets the initial value of the PUP_COUNT register to zero. It does not require a clock, it is initialized from the POF file.
