I design a board with max10,and do not design the reset input for max10, how can I generate a internal reset ?

To SREE: the initial value of PUP_COUNT is zero. Why is this a concern?

To ZLAN01: My logic generates an async reset signal which can be used to async reset registers in any clock domain. If you want a sync reset instead, just run the async reset thru a dual rank synchronizer for the specific clock domain. You may have just one, or possibly even more. So it depends on how you write your system logic (w/ async or sync reset).