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zlan01's avatar
zlan01
Icon for New Contributor rankNew Contributor
6 years ago

I design a board with max10,and do not design the reset input for max10, how can I generate a internal reset ?

Can I use the locked output of pll to generate a reset signal for my design? And what is the best reset mode for max10 ?using a input reset or generating a reset signal just in FPGA ？ For my board,t...
SreekumarR_G_Intel's avatar
SreekumarR_G_Intel
Icon for Frequent Contributor rankFrequent Contributor
6 years ago

Sure ....but my only cocnern is what is the initial value of the counter register PUP_count ?

Thank you ,

Regards,

Sree