I cant find any mistake but my compiler says its a mistake

library ieee;
use ieee.std_logic_1164.all;
use IEEE.numeric_std.all;
entity cnt is
	port 
	(
		clk		: in std_logic;
		enable	: in std_logic;
		sr_out	: out std_logic_vector(3 downto 0);
		sr_in	   : in std_logic
	);
end entity;
architecture rtl of cnt is
	-- Build an array type for the shift register
	signal sr:   unsigned(3 downto 0);
	-- Declare the shift register signal
	
begin
	process (clk)
	begin
		if (rising_edge(clk)) then
			if (enable = '1') then
			sr<=sr+1;
			end if;
		end if;
	end process;
	-- Capture the data from the last stage, before it is lost
	sr_out <= std_logic_vector(sr);
end rtl;