--- Quote Start ---
No
No
No
This is bad advice. Never use IEEE.std_logic_unsigned.all or IEEE.std_logic_signed.all. Those are non standard libraries, and cause a variety of problems, especially the day where you will need to use both signed and unsigned values in the same module.
Only use those two packages:
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
Then change the type of the signal counter to wither "signed" or "unsigned", depending on what you want, and then you can just use
counter <= counter + 1;
If you never need the actual bit representation of the signal counter you can also make it a natural or an integer. Just remember to put a fixed range on it.
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NO STILL CODE WILL HAVE SAME PROBLEM.
with library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
Please correct me if i am wrong.
i'm using QuartusII 17.0
------------------------------------
-- Quartus Prime VHDL Template
-- Basic Shift Register
library ieee;
use ieee.std_logic_1164.all;
use IEEE.numeric_std.all;
entity cnt is
port
(
clk : in std_logic;
enable : in std_logic;
sr_out : out std_logic_vector(3 downto 0);
sr_in : in std_logic
);
end entity;
architecture rtl of cnt is
-- Build an array type for the shift register
signal sr: std_logic_vector(3 downto 0);
-- Declare the shift register signal
begin
process (clk)
begin
if (rising_edge(clk)) then
if (enable = '1') then
sr<=sr+'1';
end if;
end if;
end process;
-- Capture the data from the last stage, before it is lost
sr_out <= sr;
end rtl;
-------------------------------------------------------------------------
ERROR message
Error (10327): VHDL error at cnt.vhd(36): can't determine definition of operator ""+"" -- found 0 possible definitions
Error: Quartus Prime Analysis & Elaboration was unsuccessful. 1 error, 3 warnings
Error: Peak virtual memory: 742 megabytes
Error: Processing ended: Thu Nov 02 23:28:17 2017
Error: Elapsed time: 00:01:02
Error: Total CPU time (on all processors): 00:00:41
I think Representative is correct.
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