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CHatz's avatar
CHatz
Icon for New Contributor rankNew Contributor
7 years ago

I am using the same JTAG connector to test the FPGA with System Console and to monitor signals with Signal Tap analyzer.

I cannot program the FPGA using signal tap when System Console is open. The other issue I am having is that Signal Tap analyzer won't trigger when I am accessing registers fro System Console (both t...
ShafiqY_Intel's avatar
ShafiqY_Intel
Icon for Frequent Contributor rankFrequent Contributor
7 years ago

Hi,

Can you try to change your TCK frequency to 6 MHz (default value)?

Kindly try it out with your design and let me know the result.

Thank you.😉