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直多喜川0's avatar
直多喜川0
Icon for New Contributor rankNew Contributor
6 years ago

I am using a CYCLONE IV E FPGA, but inserting a comment out statement causes a bug.

Although written in verilogHDL, inserting a comment out statement causes a problem.If you delete the comment out statement, it works normally.

3 Replies

  • Vicky1's avatar
    Vicky1
    Icon for Regular Contributor rankRegular Contributor
    6 years ago

    Hi,

    Could you please check with modifying the statement like below,

    parameter [31:0] PROMDATA_014 = 32'h3ffffa00;

    Since screenshot showing double entry for "parameter [31:0] PROMDATA_015".

    if you still have any issue please let me know with detail Error.

    Regards,

    Vikas

    • 直多喜川0's avatar
      直多喜川0
      Icon for New Contributor rankNew Contributor
      6 years ago

      Thank you for your response.

      I tried to fix it, but it was no good.

      As for the details of the error, the circuit malfunctions not related to this description.

      Is comment out not effective?

  • Vicky1's avatar
    Vicky1
    Icon for Regular Contributor rankRegular Contributor
    6 years ago

    Hi,

    I think,it`s not a good way to suggest without looking the complete code.

    Could you please provide your code? because the issue we are looking may occur from different place.

    -Thanks,

    Vikas