Forum Discussion

New Contributor

6 years ago

I am using a CYCLONE IV E FPGA, but inserting a comment out statement causes a bug.

Although written in verilogHDL, inserting a comment out statement causes a problem.If you delete the comment out statement, it works normally.

Regular Contributor

6 years ago

Hi,

Could you please check with modifying the statement like below,

parameter [31:0] PROMDATA_014 = 32'h3ffffa00;

Since screenshot showing double entry for "parameter [31:0] PROMDATA_015".

if you still have any issue please let me know with detail Error.

Regards,

Vikas