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Altera_Forum's avatar
Altera_Forum
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13 years ago

I am not sure why this happen.. (process problem)

Hi. I made two same codes about BCD adder and first code is working well, but second code had a problem.The only diffence between two code is the sensitivity list.

first code includes bin_result, and second code doesn't.

when I test the two code in Model_sim..

first code show me the bcd_result output. but second code doesn't show me the bcd_result( just show me the redline )

I want to know why first code show me the bcd_result output and second code can't!

(1)

LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL; -- Using If-else

USE IEEE.STD_LOGIC_UNSIGNED.ALL; --BCD correction adder

ENTITY bcd_adder is

PORT(

astring : in std_logic_vector(7 downto 0);

bstring : in std_logic_vector(7 downto 0);

bcd_result : out std_logic_vector(7 downto 0));

end bcd_adder;

Architecture arc of bcd_adder is

signal bin_result : std_logic_vector(7 downto 0); -- initial interconnection signal

BEGIN

bin_result<= astring + bstring; -- initial interconnection signal

PROCESS(astring,bstring,bin_result)

BEGIN

IF bin_result>"1001" -- &#47592; &#50724;&#47480;&#51901;&#48512;&#53552; LSB

THEN bcd_result <= bin_result+"00110";

else bcd_result <= bin_result;

end if;

end process;

end arc;

-------------------------------------------------

(2)

LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL; -- Using If-else

USE IEEE.STD_LOGIC_UNSIGNED.ALL; --BCD correction adder

ENTITY bcd_adder_error is

PORT(

astring : in std_logic_vector(7 downto 0);

bstring : in std_logic_vector(7 downto 0);

bcd_result : out std_logic_vector(7 downto 0));

end bcd_adder_error;

Architecture arc of bcd_adder_error is

signal bin_result : std_logic_vector(7 downto 0); -- initial interconnection signal

BEGIN

bin_result<= astring + bstring; -- initial interconnection signal

PROCESS(astring,bstring) -- Think about the reason why i include the bin_result

BEGIN

IF bin_result>"00001001"

THEN bcd_result <= bin_result+"00000110";

else bcd_result <= bin_result;

end if;

end process;

end arc;

4 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    13 years ago

    First remember that the quartus synthesizer ignores sensitivity lists, so both codes will in fact generate the same logic. This is only a simulation problem.

    Second, the rule with sensitivity lists, when you aren't doing a clocked process, is to include in the list all the signals that you read in the process. In your case, the sensitivity list should be (bin_result). It is only by doing this that you ensure that the simulator will give the same results than a real implementation.

    What is happening in (2) is probably that in your test bench affects simultaneously new values to astring and bstring, and does it only once. With this line
    bin_result<= astring + bstring;
    the bin_result signal will be updated with the new value in the simulation, but only after a delta cycle. On the other hand your process will be executed on the same delta cycle that you changed the astring and bstring signals, and at this moment bin_result still has its old value.
  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    I disagree, the sensibility list should be all signals that "feed" the process. That are all signals after the "<=" affectation or the ":=" affectation.

    Else you produce latches.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    13 years ago

    Why do you disagree? We basically say the same thing. Signals that "feed" the process and signals that are "read" in the process mean the same thing for me. And in this case the only signal "read" or "feeding" the process is bin_result.

    But I don't agree on the latches production though ;) As I said Quartus will ignore the sensitivity list and just create a pure combinational process, whatever the sensitivity list is (just try it and check RTL viewer). Latches are produced if you have one or several outputs that is only set in some paths in the process. In the code here bcd_result is always affected a value so no latch will be created.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    13 years ago

    Oh so Sorry. I didn't read carefully the code :oops:. I believed that "bin_result<= astring + bstring; -- initial interconnection signal" was inside the process.

    Quartus II ignores sensitivity list. ModelSim doesn't. ==> produce mismatch between synthesis and simulation.

    Unsure that hyeok1234 understands very well sensitivity lists.