I am not sure why this happen.. (process problem)

First remember that the quartus synthesizer ignores sensitivity lists, so both codes will in fact generate the same logic. This is only a simulation problem.

Second, the rule with sensitivity lists, when you aren't doing a clocked process, is to include in the list all the signals that you read in the process. In your case, the sensitivity list should be (bin_result). It is only by doing this that you ensure that the simulator will give the same results than a real implementation.

What is happening in (2) is probably that in your test bench affects simultaneously new values to astring and bstring, and does it only once. With this line

bin_result<= astring + bstring;

the bin_result signal will be updated with the new value in the simulation, but only after a delta cycle. On the other hand your process will be executed on the same delta cycle that you changed the astring and bstring signals, and at this moment bin_result still has its old value.