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Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
8 years ago

I am not getting expected response in Modelsim

Dear all,

Could someone please have a look at my code and say what is wrong in it.

entity pinconfig is

port(

pins :in std_logic_vector (13 downto 0):="00000000000000";

signalsin :inout std_logic_vector (35 downto 0);

signalsout :inout std_logic_vector (35 downto 0)

);

end pinconfig;

architecture behav of pinconfig is

component iobuffer

PORT

(

datain : IN STD_LOGIC_VECTOR (35 DOWNTO 0);

oe : IN STD_LOGIC_VECTOR (35 DOWNTO 0);

dataio : INOUT STD_LOGIC_VECTOR (35 DOWNTO 0);

dataout : OUT STD_LOGIC_VECTOR (35 DOWNTO 0)

);

end component;

type c is array (0 to 35, 0 to 2) of integer range 0 to 35;

signal config : c :=

((0,0,1),(1,1,1),(2,2,1),(3,3,0),(4,4,3),(5,5,0),(6,6,3),(7,7,3),(8,8,3),(9,9,3),(10,10,3),(11,11,3),

(12,12,3),(13,13,0),(14,14,3),(15,15,3),(16,16,3),(17,17,3),(18,18,1),(19,19,3),(20,20,3),(21,21,3),(22,22,3),(23,23,3),

(24,24,3),(25,25,3),(26,26,3),(27,27,0),(28,28,3),(29,29,0),(30,30,0),(31,31,0),(32,32,0),(33,33,0),(34,34,0),(35,35,3));

--signal config : c :=

--((0,27,3),(1,29,3),(2,31,3),(3,5,0),(4,4,3),(5,4,0),(6,13,3),(7,18,3),(8,8,3),(9,9,3),(10,10,3),(11,11,3),

--(12,12,3),(13,6,0),(14,14,3),(15,15,3),(16,16,3),(17,17,3),(18,7,1),(19,19,3),(20,20,3),(21,21,3),(22,22,3),(23,23,3),

--(24,24,3),(25,25,3),(26,26,3),(27,0,0),(28,28,3),(29,1,0),(30,33,0),(31,2,0),(32,34,0),(33,3,0),(34,35,0),(35,32,3));

--config(x,x,0) = out (fpga => gpio)

--config(x,x,1) = in (fpga <= gpio)

--config(x,x,2) = constant low (pin)

--config(x,x,3) = high-Z (pin)

signal temp: std_logic_vector (35 downto 0);

I Used 2 different pin configurations. Both failed

thanks

11 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor

    Hai Raj,

    I am not writing test bench . I directly compile through Quartus RTL Simulation.