I am not getting expected response in Modelsim

You dont say what the problem is?

You Didnt post the whole code?

your picture is far too small.

Not much we can say until you fix the above.

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use ieee.std_logic_unsigned.all;

use ieee.numeric_std.all;

entity pinconfig is

port(

pins :in std_logic_vector (13 downto 0):="00000000000000";

signalsin :inout std_logic_vector (35 downto 0);

signalsout :inout std_logic_vector (35 downto 0)

);

end pinconfig;

architecture behav of pinconfig is

component iobuffer

PORT

(

datain : IN STD_LOGIC_VECTOR (35 DOWNTO 0);

oe : IN STD_LOGIC_VECTOR (35 DOWNTO 0);

dataio : INOUT STD_LOGIC_VECTOR (35 DOWNTO 0);

dataout : OUT STD_LOGIC_VECTOR (35 DOWNTO 0)

);

end component;

type c is array (0 to 35, 0 to 2) of integer range 0 to 35;

signal config : c :=

((0,27,0),(1,29,0),(2,31,0),(3,5,0),(4,4,3),(5,4,0),(6,13,3),(7,18,3),(8,8,3),(9,9,3),(10,10,3),(11,11,3),

(12,12,3),(13,6,0),(14,14,3),(15,15,3),(16,16,3),(17,17,3),(18,7,1),(19,19,3),(20,20,3),(21,21,3),(22,22,3),(23,23,3),

(24,24,3),(25,25,3),(26,26,3),(27,0,0),(28,28,3),(29,1,0),(30,33,0),(31,2,0),(32,34,0),(33,3,0),(34,35,0),(35,32,3));

--signal config : c :=

--((0,0,0),(1,1,0),(2,2,0),(3,3,0),(4,4,3),(5,5,0),(6,6,3),(7,7,3),(8,8,3),(9,9,3),(10,10,3),(11,11,3),

--(12,12,3),(13,13,0),(14,14,3),(15,15,3),(16,16,3),(17,17,3),(18,18,1),(19,19,3),(20,20,3),(21,21,3),(22,22,3),(23,23,3),

--(24,24,3),(25,25,3),(26,26,3),(27,27,0),(28,28,3),(29,29,0),(30,30,0),(31,31,0),(32,32,0),(33,33,0),(34,34,0),(35,35,3));

--signal config : c :=

--((0,27,3),(1,29,3),(2,31,3),(3,5,0),(4,4,3),(5,4,0),(6,13,3),(7,18,3),(8,8,3),(9,9,3),(10,10,3),(11,11,3),

--(12,12,3),(13,6,0),(14,14,3),(15,15,3),(16,16,3),(17,17,3),(18,7,1),(19,19,3),(20,20,3),(21,21,3),(22,22,3),(23,23,3),

--(24,24,3),(25,25,3),(26,26,3),(27,0,0),(28,28,3),(29,1,0),(30,33,0),(31,2,0),(32,34,0),(33,3,0),(34,35,0),(35,32,3));

--config(x,x,0) = out (fpga => gpio)

--config(x,x,1) = in (fpga <= gpio)

--config(x,x,2) = constant low (pin)

--config(x,x,3) = high-Z (pin)

signal temp: std_logic_vector (35 downto 0);

begin

process (pins)

begin

--pins(13 downto 8) = mapped to

--pins(7 downto 2) = mapped from

--pins(1 downto 0) = out, in or high-Z

config(to_integer(unsigned(pins(13 downto 8))),1) <= to_integer(unsigned(pins(7 downto 2)));

config(to_integer(unsigned(pins(13 downto 8))),2) <= to_integer(unsigned(pins(1 downto 0)));

end process;

process (signalsin, signalsout)

begin

case config(0,2) is

when 0 => temp(config(0,0)) <= signalsin(config(0,1));

when 1 => temp(config(0,1)) <= signalsout(config(0,0));

when others =>

end case;

case config(1,2) is

when 0 => temp(config(1,0)) <= signalsin(config(1,1));

when 1 => temp(config(1,1)) <= signalsout(config(1,0));

when others =>

end case;

case config(2,2) is

when 0 => temp(config(2,0)) <= signalsin(config(2,1));

when 1 => temp(config(2,1)) <= signalsout(config(2,0));

when others =>

end case;

case config(3,2) is

when 0 => temp(config(3,0)) <= signalsin(config(3,1));

when 1 => temp(config(3,1)) <= signalsout(config(3,0));

when others =>

end case;

case config(4,2) is

when 0 => temp(config(4,0)) <= signalsin(config(4,1));

when 1 => temp(config(4,1)) <= signalsout(config(4,0));

when others =>

end case;

--here i have to write code for all 36bpins, but i cannot write a reply to you more than 10000

when others =>

end case;

end process;

process (temp)

begin

case config(0,2) is

when 0 => signalsout(config(0,0)) <= temp(config(0,0));

when 1 => signalsin(config(0,1)) <= temp(config(0,1));

when 2 => signalsout(config(0,0)) <= '0';

when others => signalsout(config(0,0)) <= 'Z';

end case;case config(1,2) is

when 0 => signalsout(config(1,0)) <= temp(config(1,0));

when 1 => signalsin(config(1,1)) <= temp(config(1,1));

when 2 => signalsout(config(1,0)) <= '0';

when others => signalsout(config(1,0)) <= 'Z';

end case;case config(2,2) is

when 0 => signalsout(config(2,0)) <= temp(config(2,0));

when 1 => signalsin(config(2,1)) <= temp(config(2,1));

when 2 => signalsout(config(2,0)) <= '0';

when others => signalsout(config(2,0)) <= 'Z';

end case;case config(3,2) is

when 0 => signalsout(config(3,0)) <= temp(config(3,0));

when 1 => signalsin(config(3,1)) <= temp(config(3,1));

when 2 => signalsout(config(3,0)) <= '0';

when others => signalsout(config(3,0)) <= 'Z';

end case;case config(4,2) is

when 0 => signalsout(config(4,0)) <= temp(config(4,0));

when 1 => signalsin(config(4,1)) <= temp(config(4,1));

when 2 => signalsout(config(4,0)) <= '0';

when others => signalsout(config(4,0)) <= 'Z';

--here i have to write code for all 36bpins, but i cannot write a reply to you more than 10000

when others => signalsout(config(35,0)) <= 'Z';

end case;

end process;

end behav;

Have a loot and help me

Picture is still too small

You didnt say what this code is meant to do, or whats wrong?

Commenting on what code you did post - it is pretty bad - big arrays full of constants with no explanations of what they are. Especially when you didnt say what the code does or whats wrong with the code.

--config(x,x,0) = out (fpga => gpio)

--config(x,x,1) = in (fpga <= gpio)

--config(x,x,2) = constant low (pin)

--config(x,x,3) = high-Z (pin)

these are the config rules I used. And this program is pinconfiguration of the FPGA TO GPIO and GPIO TO FPGA. ALTBIO (Bidirectional buffer) I used here. And I am trying to develop the module for FPGA to configure faster and run faster. But I could not able to see expected output in model sim.

Hi,

Are you trying to tell that bidirectional pin's are not responding after forcing input to it?

If yes, in test bench while changing config you should set the bidirectional pins to noforce.

can you post a portion of test bench code?

Best Regards,

Anand Raj Shankar

(This message was posted on behalf of Intel Corporation)

Hi Sasi,

Your simulation is not acting as you would expect from your source code. This is a clear hint for missing signals in a process sensitivity list.

After a brief look on your posted code, your second and third process is missing "case_config" in its process sensitivity list.

If you have a look at the synthesis report, you should find a warning about missing signals in the sensitivity list as well.

Best,

Jusuf