I am looking for a way to initialize the E-tile PAM4 PMA and get it to work properly.

Hi,

I am currently developing firmware and driver for E-tile transceiver PHY IP on Intel® Agilex™ FPGA F-Series 027(AGFB027).

My FPGA logic development colleague, who has previously worked on Xilinx FPGA development, told me that we need to use the HPS such as A53 Linux driver to initialize the E-tile for it to work properly. However, I have not been able to find any relevant driver program online.

I have referred to the "E-tile Hard IP User Guide E-Tile Hard IP for Ethernet and E-Tile CPRI PHY Intel® FPGA IPs.pdf" and "ug_etile_xcvr_phy-683723-667139.pdf" articles and have completed the Linux driver code according to the description (yet to be tested on the board).

I am puzzled that this IP core has been around for a long time, but I cannot find any relevant Linux or bare-metal driver programs online. Is it possible that my FPGA logic development colleague has misunderstood something?

So I want to know what steps can I follow to bring up the E-tile PAM4 PMA on Intel® Agilex™ E-tile design? Is it done through software driver initialization to make it work properly, or can the logic configure the IP core internally through HDL?

Thanks.