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Altera_Forum
Honored Contributor
9 years agoHuge numbers of recovery failures - even though reset is on Global Clock Net
Hi All Ive raised a mysupport ticket on this - but I thought I might ask here also. I have a Stratix iV design that has 91% logic utilisation. We are in the process of cleaning up our reset str...
Altera_Forum
Honored Contributor
9 years agoPhysical synthesis, as you mention, may fix the problem, though it will greatly increase compile time. If you must use a global, you may want to see if you should be using a different clock control block. That insertion delay (the time to get to the clock control block) is pretty long (4.1 ns), so you should check to see if the Fitter selected the closest clock control block for getting the reset on the global clock.