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Altera_Forum
Honored Contributor
Honored ContributorHuge numbers of recovery failures - even though reset is on Global Clock Net
Hi All Ive raised a mysupport ticket on this - but I thought I might ask here also. I have a Stratix iV design that has 91% logic utilisation. We are in the process of cleaning up our reset str...
Altera_ForumHonored Contributor
Honored ContributorOk - Ive found this interesting page:
http://quartushelp.altera.com/15.0/mergedprojects/logicops/logicops/def_physical_synthesis_asynchronous_signal_pipelining.htm Anyone know if I can determine if a signal is dertermined to be "critical"? The Pipeline asynchronous signal option is enabled in project settings - and it seems to fit with my problem exactly.
