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Altera_Forum's avatar
Altera_Forum
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9 years ago

Huge numbers of recovery failures - even though reset is on Global Clock Net

Hi All Ive raised a mysupport ticket on this - but I thought I might ask here also. I have a Stratix iV design that has 91% logic utilisation. We are in the process of cleaning up our reset str...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
9 years ago

The modern advice is "use reset only when required" but if already done then reduce fan out by pipelining reset assuming your design accepts it. Modules that wait for signals e.g. at end of chain can have pipelined reset unless they send hand shake signals. In fact if your design gets active well after reset release you can set false path all over.