Huge frequency error in Altera NCO

Hello all,

I have a problem with a simple design in a Cyclone V SoC and I cannot see what's the error. The design is in the picture shown bellow.

It is an NCO implemented in the FPGA logic, which is driven by a 96 MHz clock generated through a PLL whose reference clock is the hps2fpga_user0_clock.

The NCO data output and a signal clock (with the same frequency and phase as the one used for the NCO logic) are sent to a DAC, so I can measure the analog version with a Spectrum Analyzer.

If the NCO is configured to generate a sinusoid of a couple of hundred kilohertz, I can see a tone with the same frequency as expected. However, If the NCO is configured to generate a sinusoid of about a megahertz, then the real tone has an error of tens or hundreds hertz. Moreover, the error is no constant by the tone continuously moving in frequency.

NCO is multiplier-based, and phase accumulator is 32 bits so frequency resolution should be 0,02 hertz. I think that maybe dac_clock signal does not arrive at DAC in the middle of data, so it is not sampled correctly. I am trying to figure out how to specify these timing requirements in Quartus II.

Does anybody have any idea of how to solve it?

http://www.alteraforum.com/forum/attachment.php?attachmentid=12624&stc=1