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Altera_Forum
Honored Contributor
Honored ContributorHS_LVDS in signal tap
Greetings once again. I am still running into problems trying to lower the clock speed of ALTLVDS megafunction. I am trying to look at some of the clocks and this one, coming out of a startix II GX P...
Altera_ForumHonored Contributor
Honored ContributorI think, the error message is rather clear and pretty self-explanatory. Signal tap can only access signals available for connection in the logic fabric. Dedicated SERDES clock signals aren't as well as serial SERDES in- and outputs aren't.
