Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

HPS2FPGA bridge throughput

Hi everybody, I am currently playing around with the Cyclone V SoC Development board. I have a QSys system running resembling the Golden system reference design apart from the fact that the h...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

Some memcpy implementations use 32-bit copy operations, and if the CPU has a data cache it will cause burst transfers, but it is still slower than a DMA solution as I'd say you'd need about 10 CPU cycles for each 32-bit transfer (maybe a Nios II guru will correct this figure).

If the source or destination isn't 32-bit aligned, memcpy will most probably revert to 8-bit transfers anyway.