HPS Gbit PHY access from FPGA

I'm a beginner at this myself, but so far from what I've gathered, you wouldn't want to access the Ethernet PHY from the FPGA side. The Ethernet MAC is a SOC element connected to the ARM cores. The MAC controls the PHY. If you want to send/receive data over Ethernet, you should write FPGA code to place/get your data into memory. You would then trigger an interrupt to the ARM. It then runs the TCP/IP stack. Implementing Ethernet in FPGA code takes a lot of resources. You have a perfectly good Ethernet in the processor side.