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tesla's avatar
tesla
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4 years ago

HPS and FPGA reset

Hi everybody! I’m working on Arria 10 SoC and I want to verify it is possible to reset the HPS from the FPGA design (per state machine in the FPGA) and to verify it is possible to load the FPGA in...
sstrell's avatar
sstrell
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4 years ago

So you have an HPS boot-first scenario set up and it's trying to reprogram the FPGA on reset. I'm thinking that a warm reset of the processor (instead of cold) would prevent this, but I'm not sure. You'll need to go into the HPS parameters and make adjustments (don't have it open right now so I can't tell you what to change) and regenerate the bootloader.

tesla's avatar
tesla
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4 years ago

Hi @sstrell ,

Tried with both warm and cold resets but nothing seems to work. Anyway is it possible avoid reset of FPGA DDR when HPS reset is issued ?

Because when I write some data to FPGA DDR and read after reset in uboot or reboot in kernel, it will be erased and reads back as 0x0.