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tesla's avatar
tesla
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4 years ago

HPS and FPGA reset

Hi everybody! I’m working on Arria 10 SoC and I want to verify it is possible to reset the HPS from the FPGA design (per state machine in the FPGA) and to verify it is possible to load the FPGA in...
tesla's avatar
tesla
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4 years ago

Hi @sstrell ,

For my first question I could see the options as you mentioned in your post and I enabled to use it, but how can I control these reset signals from FPGA design. Could you please brief on this by giving some real-time example?

Coming to my second question, I need to understand how h2f_reset (in my design this acts as hard/soft reset) will affect FPGA fabric though it is not connected to any FPGA IPs.

Please clarify.

Thanks.

sstrell's avatar
sstrell
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4 years ago

You have the f2h resets connected, what you're highlighting in your screenshot. To use them, just enable reset from some logic on the FPGA side, whatever you have connected. Or export them out of the Platform Designer system and connect them to other control logic. They're just control signals, nothing fancy. Of course, go through the HPS documentation to understand what gets reset in the HPS for either cold or warm reset.

For h2f reset, this is a reset you would connect up to your FPGA design (you already have it exported out of the system in the screenshot) and control through software running on the processor, either bare metal or higher up (application running in Linux perhaps).