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#1 You can't move the location of the H2F bridge, the HPS is an ASIC so you can't move the base addresses around like soft logic in Qsys. The only way to address more than 960MB of address space on the other side of the H2F bridge is to include the address span expander in the Qsys system and page the memory.
# 2 Qsys has no idea that the HPS can only address 960MB of memory from the H2F bridge master port. This is a limitation of the HPS. The only thing I could see being feasible is for the HPS component to issue the warning by querying Qsys to tell it how much memory is connected to the master then error out if it exceeds 960MB. That said I think I would be annoyed if I saw that message after hooking up 1GB of SDRAM to that bridge since I would be ok with not making 64MB of that memory directly accessible to the HPS. If I had logic in the FPGA that needs access to the same memory that 64MB at the end that is not directly accessible to the HPS can still be accessed by logic in the FPGA.
# 3 In the L2 cache there is a programmable window that determines whether transactions route to the L3 interconnect (M0) or to the SDRAM (M1). The window sets the start and end address (in 1MB chunks) a range that gets routed to the SDRAM. For example if I want the MPU have 3GB of HPS SDRAM visible to it I would set the start at address 0x0 and the end to 0xC000_0000. That means any time either processor accesses addresses in the lower 3GB of the address space they all will be routed to the SDRAM instead of the L3 interconnect. The HPS MPU chapter describes this mechanism in more detail.
# 4 If I understood the question correct, when you access the HPS memory space from the FPGA it's exposed as a full 4GB through the F2H bridge. The reason why you see this connection paired with an address span expander is if your master in the FPGA only supports a 4GB address space, connecting it directly to the HPS will prevent it from being connected to anything else (you used up it's full 4GB address space on the HPS connection). So the address span expander let's you implement a paging system to minimize how much address span is downstream from the master connected to it. For example if I wanted Nios II to be able to access the 4GB HPS address space I might setup the address span expander to have a 128MB window that I can move around so that Nios II only has access to a 128MB page into the total 4GB address space inside the HPS. That's why I was saying for# 1 you could use a similar technical to expand the addressing capabilities of the H2F bridge. Keep in mind you have to maintain the address span extender window in software and it's not a good idea to move that window when there are outstanding transactions.[/QUOTE
Dear badOmen
I use cycone V board with 2GB sdram, i cofigure the preloader and u-boot to have 2GB sdram also.
I cant write with memtool to address from 0x80000000 to 0xc0000000 - i have error massage
root@socfpga_cyclone5:~# echo 1 > /sys/class/fpga-bridge/lwhps2fpga/enable
root@socfpga_cyclone5:~# echo 1 > /sys/class/fpga-bridge/hps2fpga/enable
root@socfpga_cyclone5:~# echo 1 > /sys/class/fpga-bridge/fpga2hps/enable
root@socfpga_cyclone5:~# memtool -32 0x80000000=0x00200100
Writing 32-bit value 0x200100 to address 0x80000000
[ 6839.386707] Unhandled fault: external abort on non-linefetch (0x1818) at 0x76fd3000
Bus error
and i know it is related to preloader only (if i use older preloader - 13.1 it works O.K)
how can i set the start address and end address as mentioned before at q3.
i use quartus 14.1 or 15.0 and with both i have the same error
thanks a lot
yehuda
Honored Contributor
