how tooutput a high speed clock

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I need change the ADC clock to control sampling rate(we are designing a digital storage osciioscope). I just need a 1M time Sampling clock and 200M Equivalent Sampling,so I need a clock from FPGA. I just change the ADC clock's frenquency to get different sampling rate.

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If you are designing an oscilloscope, then the number of bits in your ADC, and the highest sampling frequency determine your required jitter. For example, if your ADC is 12-bits, and the maximum frequency is 100MHz, then the maximum jitter (clock plus ADC) is

tj < 1/(2*pi*fmax*2^B ) = 1/(2*pi*100MHz*2^12) = 0.39ps

Which is a difficult specification to meet. You would generally use an external clock source (low jitter crystal or VCO) to implement such a clock.

Why do you want to implement an equivalent sampling scheme at 200MHz? This is a low enough frequency that you can implement a real-time sampling oscilloscope. There's no advantage in trying to achieve equivalent time sampling at this frequency, as you still need to meet the analog input bandwidth and jitter specification of a real-time sampling scope.

Cheers,

Dave

I'm just a beginner and not familar with FPGA.My problem is that I don't how to deal with the signal of FPGA including input and output. I used a comparator to deal with the clock from FPGA.Is there other solution to deal with it.

Thank you very much

FPGA IO signals can't be good or bad as such. They undergo the general rules of interfacing high speed digital signals. As you are talking about 1 MHz clock frequency, I guess, the problem may be, that you aren't familar with logic signals in the FPGA typical speed range.

A good standard to get clean square waves is using source side impedance matching. Presumed you have a cable or PCB trace with e.g 50 to 80 ohm characteristic impedance, supplement the FPGA pins output impedance with a series resistor to make the sum match the characteristic impedance. The method will work with a low to moderate capacitive load.

For a detailed discussion, you should tell more about the problem you're facing. Posting waveform photos isn't a bad idea.

P.S.: For high performance requirements, e.g. to achieve low jitter, it may be reasonable, to send the clock signal using the LVDS IO standard and place a LVDS receiver near the load. This will effectively eliminate most common mode interferences possibly present in a highly populated digital circuit.

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I need a clock to control high speed AD.But I measure it with oscillograph finding it is very bad so that AD can't work.

thank you very much

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Bad in what sense? Is it due to incompatible voltage levels (for example ADC is expecting clock in LVPECL standard and FPGA is outputting 3.3V LVCMOS) or due to high clock jitter?

Normally you would not want to clock high performance ADC from FPGA, because FPGA output clocks have relatively high jitter.

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I need a clock to control high speed AD.But I measure it with oscillograph finding it is very bad so that AD can't work.

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What clock rate is your ADC?

The design documents here;

http://www.ovro.caltech.edu/~dwh/carma_board/

Discuss the design of a 1GHz ADC.

If you can provide more detail, I can offer suggestions.

Cheers,

Dave