Honored ContributorDear all,
How to write user logic to control a SOPC DMA controller ? without Nios II? So it is a Avalon Memory Mapped Master, connect to slave port of the DMA controller, but how to initilize DMA controller by this user logic? How to write the control word, start address, DMA LENGTH to the registers by user logic? which signals on the Avalon fabric should I use? Thank you very much!
Honored ContributorHave a look at the avalon specification (http://www.altera.com/literature/manual/mnl_avalon_spec.pdf). It describes all the signals and timings in Avalon busses.
You'll probably need to write a state machine that can write all the registers one by one.Honored ContributorCould you give more details or examples on how to write to the registers?
Where can I find DMA register's address? where I can find more information about DMA's control port slave? The DMA core manual says "An Avalon-MM master peripheral sets up and initiates DMA transactions by writing to registers via the control port. The master peripheral then sets a bit in the control register to initiate the DMA transaction." Thank you very much! --- Quote Start --- Have a look at the avalon specification (http://www.altera.com/literature/manual/mnl_avalon_spec.pdf). It describes all the signals and timings in Avalon busses. You'll probably need to write a state machine that can write all the registers one by one. --- Quote End ---Honored ContributorThe DMA registers' addresses are described in the DMA's datasheet. To read or write them, you need to create an Avalon master interface on your component, place the address you want to access on the address signal, perform the operation by enabling the read or write signal, and wait until wait request is 0.
Honored ContributorThere is no registers's addresses in the datasheet, only Register map,
it says "Programmers using the HAL API never access the DMA controller hardware directly via its registers. In general, the register map is only useful to programmers writing a device driver.The Altera-provided HAL device driver accesses the device registers directly" Does it mean can we write them directly? Thank you very much! --- Quote Start --- The DMA registers' addresses are described in the DMA's datasheet. To read or write them, you need to create an Avalon master interface on your component, place the address you want to access on the address signal, perform the operation by enabling the read or write signal, and wait until wait request is 0. --- Quote End ---Honored ContributorYes you can write the registers directly. You can get their address from the register map. First get the component base address in SOPC builder, and then add to it the register's number multiplied by 4.
As an example if the component address is 0x00001000, you can access register 0 at address 0x00001000, register 1 at address 0x00001004, register 2 at address 0x00001008 etc... This is the address that you must use on the Avalon memory mapped master interface.Honored ContributorWe tried to implement such a control logic.
When we connect the logic with DMA controller in Qsys, it is reported that "Error: System.dma_0.control_port_slave: Master vga_dmalogic_0.dma_ctl does not have a waitrequest signal. Slave must match master's read and write wait time (read:1 write:0)" However there is no texture mentioned read and write wait time requests for dma controller in its datasheet. Do you have ever meet this problem? --- Quote Start --- Yes you can write the registers directly. You can get their address from the register map. First get the component base address in SOPC builder, and then add to it the register's number multiplied by 4. As an example if the component address is 0x00001000, you can access register 0 at address 0x00001000, register 1 at address 0x00001004, register 2 at address 0x00001008 etc... This is the address that you must use on the Avalon memory mapped master interface. --- Quote End ---Honored ContributorThey are usually not documented. When you write an Avalon Master it is a lot safer to implement the waitrequest signal instead (in fact I thought it was mandatory!). Then you don't have to worry about cycle lengths, you just hold your read or write control signals until waitrequest is deasserted.
Honored ContributorThank you, I would implement waitrequest then.
Altera should tell us how to write my own control logic for their IP cores.Honored ContributorThey do tell it, in the avalon specification (http://www.altera.com/literature/manual/mnl_avalon_spec_1_3.pdf). On pages 3-22 to 3-26 you will see the different transfer types with time diagrams. If you look at page 3-21 you will see that the waitrequest message is indeed required on an Avalon Master interface.
Honored ContributorGot it, thank you. I didn't notice that before.
