How to write Transfer function using QUARTUS II

That's not a particularly a Quartus problem. Your question refers to digital signal processing basics. How s-domain transfer functions translate to z-domain, how z-domain functions are implemented as differential equations. Finally how to choose a suitable number format (preferably fixed point), how to code it in HDL.

IMHO, a good text book covering all aspects is digital signal processing with fpga by Maeyer-Baese.

P.S.: There are also special high-level tools like Altera DSP builder (based on Matlab). I think, you should refer to generic HDL signal processing.

I did upload a whitepaper in the discussion thread around PID controllers:

http://www.alteraforum.com/forum/showthread.php?t=33192&highlight=pid+controller

Additionally, the question that you ask is confusing. HDL design (VHDL or System Verilog) captures a hardware design; the hardware design being reflective of whatever algorithm that you are implementing. So there are numerous technology steps:

1. Matlab/Simulink/Python/C model of your controller + plant or general dynamical system model

2. Transform to digital domain of the controller (say bilinear Z transform)

3. General digital architecture planning for the controller

4. Fixed point mathematics precision (say 16 or 24 bits)

5. HDL Coding

6. HDL Testbench

7. Refinement

8. System Testing

Sir,

thank you for your kind response

I used HDL workflow Advisor (Matlab 2012a) to generate HDL code there I can easily convert a transfer function into HDL but in Quartus I'm facing this problem.

@james bonanno (http://www.alteraforum.com/forum/member.php?u=23400):

Sir,

yes I'm little bit confuse due to the following reasons

1. In Matlab I successfully generate some code and check with co-simulation result but can not find out how to download that code into FPGA kit (Altera Cyclone EP1C12Q240C8)

2. I want input(/output) to(/from) some specific pins but can not solve this problem. (actually I'm facing this problem with Altera also when a signal requires more than one bit say a 8bit adder output)

Hence I switch over to Altera Quartus II(vary much new to Altera Quartus)

would you like to give me a way to solve it

With Regards

Kingsuk

My System:

os: Windows xp (sp2) 32bit

Matlab : 2012a (32 bit)

Altera Quartus II 11.0sp1 Web Edition (32bit)

Modelsim 10.0c SE

FPGA kit : Altera Cyclone EP1C12Q240C8