How to verify timing for Agilex DDR4 Post Layout

Please provide guidance on how Intel recommends to perform timing closure analysis. I thought I would be able to use their DDRx Batch Mode Wizard but it is seeming increasingly that this is not what Intel intended.

I've now got SPICE models that are supposed to help me perform the timing Analysis, but the DDR simulation tool in Hyperlynx doesn't require SPICE models in order to run. Additionally I now have a .dat file that has timing spec information but don't know where to apply that either

I am new to this and am not finding sufficient guidance on how to verify my design based on the Design Guideline.