Forum Discussion
New ContributorHow to verify timing for Agilex DDR4 Post Layout
Hi,
Quartus no longer perform the timing analysis on DDR based on pcb characteristics for Agilex devices.
You should follow the routing guideline and skew matching guidelines from the UG.
- https://www.intel.com/content/www/us/en/docs/programmable/683216/23-2-2-7-1/single-rank-x-16-discrete-component-topology.html
- https://www.intel.com/content/www/us/en/docs/programmable/683216/23-2-2-7-1/skew-matching-guidelines-for-ddr4-discrete.html
Regards,
Adzim
New ContributorHi,
I am using an F-series Agilex part. The DDR4 will be running off both Fabric and HPS pins.
That being said I have run into the timing closure chapter before but didn't find it useful particularly because I did not know how to export my design to touchstone file. After your response I have investigated further and found that Hyperlynx does export S-parameter files (yay!) but still need to investigate how to do it properly. Is there help on doing this?
I was hoping a .v file could be generated directly from the Quartus EMIF IP because that would allow me to do the timing analysis within Hyperlynx with their DDR analysis tool.
