Forum Discussion
New ContributorHow to verify timing for Agilex DDR4 Post Layout
Hi,
Quartus no longer perform the timing analysis on DDR based on pcb characteristics for Agilex devices.
You should follow the routing guideline and skew matching guidelines from the UG.
- https://www.intel.com/content/www/us/en/docs/programmable/683216/23-2-2-7-1/single-rank-x-16-discrete-component-topology.html
- https://www.intel.com/content/www/us/en/docs/programmable/683216/23-2-2-7-1/skew-matching-guidelines-for-ddr4-discrete.html
Regards,
Adzim
Super ContributorYou don't mention whether this is F, I or M-series, but here's the chapter on timing closure for F and I series: https://www.intel.com/content/www/us/en/docs/programmable/683216/23-2-2-7-1/f-series-and-i-series-fpga-emif-ip-i.html
And for M-series: https://www.intel.com/content/www/us/en/docs/programmable/772538/24-3-1/m-series-fpga-emif-ip-timing-closure.html
And the DDR4 board design guidelines: https://www.intel.com/content/www/us/en/docs/programmable/683216/23-2-2-7-1/ddr4-board-design-guidelines.html and https://www.intel.com/content/www/us/en/docs/programmable/772538/24-3-1/ddr4-board-design-guidelines.html.
Why would the timing report be generated as a Verilog (.v) file?
Since most of the IP is now completely hardened, you really have to rely on board simulations to guarantee your design as you have found. Is something missing from the board design guidelines chapters that you are looking for?
