How to use up all cells in an FPGA?

LFSR will do and another possible simple filler code is running several counters together then testing their equality.

type my_array is array(1 to 10) of integer range(0 to 255);
signal counter: my_array;
 
signal flag : std_logic_vector(9 downto 1);
......
process(reset,clk)
begin
if reset = '1' then
    counter <= (others => 0);
    flag <= (others => '0');
elsif rising_edge(clk) then
 
    for i in 1 to 10 loop
        counter(i) <= counter(i) + 1;
    end loop;
 
    for i in 1 to 9 loop
         if counter(i) = counter(i+1) then
             flag(i) <= '0';
         else
             flag(i) <= '1';
         end if;
    end loop;
 
end if;
end process;
 
alarm <= '1' when flag /= "000000000" else '0';--may need latching