How to use up all cells in an FPGA?

MAX II has non-volatile (flash) configuration storage. Corruption of configuration memory would be the most likely radiation effect, but can be easily detected by a verify.

Regarding the suggested test, even if all logic elements are utilized in a design, the routing resources can't. So you can't achieve a 100% test anyway. Statistical considerations suggest however, that the significance of your test doesn't change much if you have 95% or 100% utilisation. Thus you should rather think about a test design that allows easy and complete verification of it's results rather than 100% utilisation.

Two identical LFSR with a comparison of both outputs can be starting point. You can add some arbitrary operations on the output numbers to fill up the logic array.