How to use Transceiver PHY 12 port

Hi- Everyone
I'm designing a Transceiver PHY 12 port.
Transceiver PHY 11 port is passed!
It is composed of Transceiver PHY IP 1, Transceiver PHY PLL IP 1, Transceiver PHY Reset IP 1
So, I hav used PHY IP 11, PLL IP 11, Reset IP 11

But if I add one more port, I get an error.

That is, if I add one more Transceiver, I get an error.
fpll, ATX pll, and CMU pll, but the results are the same.
Which part of the code is wrong?

Error Message is below...

Error(14996): The Fitter failed to find a legal placement for all periphery components
Info(14987): The following components had the most difficulty being legally placed:
Info(175029): auto-promoted clock driver u3_A10_XCVR_native|xcvr_native_a10_0|g_xcvr_native_insts[1].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|out_pld_pcs_tx_clk_out~CLKENA0 (14%)
Info(175029): auto-promoted clock driver u10_A10_XCVR_native|xcvr_native_a10_0|g_xcvr_native_insts[1].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|out_pld_pcs_tx_clk_out~CLKENA0 (14%)
Info(175029): auto-promoted clock driver u3_A10_XCVR_native|xcvr_native_a10_0|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|out_pld_pcs_tx_clk_out~CLKENA0 (7%)
Info(175029): auto-promoted clock driver u10_A10_XCVR_native|xcvr_native_a10_0|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|out_pld_pcs_tx_clk_out~CLKENA0 (7%)
Info(175029): HSSI_DUPLEX_CHANNEL_CLUSTER ePI_tx8[0]~CLUSTER~HSSI_TX_CHANNEL_CLUSTER14~HSSI_DUPLEX_CHANNEL_CLUSTER14 (5%)
Info(175029): auto-promoted clock driver u4_A10_XCVR_native|xcvr_native_a10_0|g_xcvr_native_insts[1].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|out_pld_pcs_tx_clk_out~CLKENA0 (5%)
Info(175029): auto-promoted clock driver u8_A10_XCVR_native|xcvr_native_a10_0|g_xcvr_native_insts[1].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|out_pld_pcs_tx_clk_out~CLKENA0 (5%)
Info(175029): HSSI_DUPLEX_CHANNEL_CLUSTER ePI_tx12[0]~CLUSTER~HSSI_TX_CHANNEL_CLUSTER22~HSSI_DUPLEX_CHANNEL_CLUSTER22 (5%)
Info(175029): auto-promoted clock driver u5_A10_XCVR_native|xcvr_native_a10_0|g_xcvr_native_insts[1].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|out_pld_pcs_tx_clk_out~CLKENA0 (5%)
Info(175029): auto-promoted clock driver u9_A10_XCVR_native|xcvr_native_a10_0|g_xcvr_native_insts[1].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|out_pld_pcs_tx_clk_out~CLKENA0 (5%)
Error(14986): After placing as many components as possible, the following errors remain:
Error(175001): The Fitter cannot place 1 HSSI_PMA_CGB_MASTER,
which is within Transceiver ATX PLL Intel Arria 10/Cyclone 10 FPGA IP
XCVR_ATX_PLL1_altera_xcvr_atx_pll_a10_180_qyya5ty.
Info(14596): Information about the failing component(s):
Info(175028): The HSSI_PMA_CGB_MASTER name(s):
u0_XCVR_ATX_PLL|xcvr_atx_pll_a10_0|a10_xcvr_atx_pll_inst|twentynm_hssi_pma_cgb_master_inst
Error(16234): No legal location could be found out of 8 considered location(s).