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Altera_Forum
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15 years ago

How to use the DCFIFO?

Hello i used the megawizard to instantiate a DCFIFO but it seems i can't write anything to the fifo.. my usedw never changes

Anyone has a verilog example of a code that is working??? I tried to let wrreq always at 1 and wrclck changes when i need to write something

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  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    My assumption is that your fifo gets full.

    When the fpga starts and soon after reset, you are writing into the fifo without reading thus it gets full and the word count will increase from 0 to 128. When 128 the word count cannot represent 128 and rolls back to zero unless you have one extra bit on your word count.

    The best way is to simulate your design or trigger the signaltap when fifo words is say half (bit[5] '0' => '1')
  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    it could be just overflowing with word counter rolled over

  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    Hum it's true but i've tried outside the block and it doesnt work also.

    I used signal tap to debug but my USEDW never changes, the last 2 signals are the wrusedw and wrdusedw

    The clk is working, wrreq is always at 1, data in is working allright but my usedw never changes. why?
  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    several issues but I see that when your counter is == 10 the word count may not coincide with wordcount[2] == 1

    {count 0 ~ 10}means 10~11 words = 1010 or 1011
  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    Here is my wrapper. Please help!

    My valid never goes to 1.

    My rdclk is at 50mhz (duno if that matters, i guess not) 

    module fifowrapper(
                    // inputs:
                     rdclk,
                            rstn,
                            rdreq,
                    // outputs:
                     valid,
                     q
                  );
                        
input  rdclk;
input rdreq;
input rstn;
reg wrclk;
reg wrreq;
output  q;
output reg valid;
wire  data;
reg  data_in;
assign data = data_in;
wire  usedw;
reg usedw_r;
assign usedw = usedw_r;
reg  counter;
always@(posedge rdclk or negedge rstn)
  if (~rstn)
   begin
   valid <= 0;
   wrreq <= 0;
   contador <= 0;
   data_in <= 0;
   wrclk <= 0;
   end
  else
begin
    counter<= counter+1;
//    valid <= 0;
//    rdreq <= 1;
    wrreq <= 1;
//    wrclk <= 0;
        if(counter== 10) //1seg
        begin
           if(usedw_r==1)
                valid <= 1;
            counter<= 0;
            data_in <= data_in + 1;
//            wrreq <=1;
//            valid <= 1;
        end
//        if (usedw_r==1)
//        begin
    //    valid <= 1;
    //    end
    
end
base    fifo_inst (
    .data ( data ),
    .rdclk ( rdclk ),
    .rdreq ( rdreq ),
    .wrclk ( rdclk ),
    .wrreq ( wrreq ),
    .q ( q ),
//    .rdempty ( rdempty_sig ),
//    .rdusedw ( usedw ),
    .wrusedw ( usedw )
//    .wrfull ( wrfull_sig )
    );
endmodule