Honored Contributor
Honored ContributorHere is my wrapper. Please help!
My valid never goes to 1. My rdclk is at 50mhz (duno if that matters, i guess not)module fifowrapper(
// inputs:
rdclk,
rstn,
rdreq,
// outputs:
valid,
q
);
input rdclk;
input rdreq;
input rstn;
reg wrclk;
reg wrreq;
output q;
output reg valid;
wire data;
reg data_in;
assign data = data_in;
wire usedw;
reg usedw_r;
assign usedw = usedw_r;
reg counter;
always@(posedge rdclk or negedge rstn)
if (~rstn)
begin
valid <= 0;
wrreq <= 0;
contador <= 0;
data_in <= 0;
wrclk <= 0;
end
else
begin
counter<= counter+1;
// valid <= 0;
// rdreq <= 1;
wrreq <= 1;
// wrclk <= 0;
if(counter== 10) //1seg
begin
if(usedw_r==1)
valid <= 1;
counter<= 0;
data_in <= data_in + 1;
// wrreq <=1;
// valid <= 1;
end
// if (usedw_r==1)
// begin
// valid <= 1;
// end
end
base fifo_inst (
.data ( data ),
.rdclk ( rdclk ),
.rdreq ( rdreq ),
.wrclk ( rdclk ),
.wrreq ( wrreq ),
.q ( q ),
// .rdempty ( rdempty_sig ),
// .rdusedw ( usedw ),
.wrusedw ( usedw )
// .wrfull ( wrfull_sig )
);
endmodule
