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Honored Contributor
Honored ContributorHow to use Shared pll in LVDS transmiter and resceiver functions
Hi, I am trying to use the shared pll function for LVDS transmiter and resceiver. AN479 says transmiter and resceiver must use the same input clock frequency. does it mean the tx_inclock of tran...
Altera_ForumHonored Contributor
Honored ContributorHi,
I should have said "use CDR". It is there for you in lvds instant. I believe - now - you may have misunderstood which clk is the ref clk for your internal PLL and which are parallel data clks According to my experience with lvds(stratix II): The rxin_clk and txin_clk are the ref clks and have to be connected both to the ref frequency. There should be no serial data clk from or into the lvds. The lvds gives you parallel clks only. You will need these parallel clks on either side(tx/Rx) to clk your data into the lvds tx for serialisation and to read your desrialised data from the lvds rx.
