How to use Shared pll in LVDS transmiter and resceiver functions

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In my design,

for LVDS Transmiter, the tx_inclock is 40MHz, deserialization factor is 20, so tx_outclock is 800M .

for LVDS Receiver, it will receive signal from the LVDS Transmiter.thus,rx_inclock should be 800M, deserialization factor is 20, rx_outclock is 40MHz.

So, the tx_inclock and rx_inclock are different in my design, how can i use the shared PLL function to reduce the resource usage. Thanks!

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I don't understand your reasoning. The serdes naturally implies a difference between "serial bit clock" (800MHz) and parallel clk(40MHz) since each 20 bits are processed in parallel. Can you explain further please...

The ref clk need not be equal to bit clk or the parallel clk