How to use Shared pll in LVDS transmiter and resceiver functions

According to the LVDS MegaFuction User Guide, rx_inclock is the receiver reference input clock. It can be exepected as an integer fraction of the bit rate, but very unlikely 800 MHz.

The more interesting question is, how you want to synchronize the receiver with the peer transmitter and where the latter is clocked from. It's also not said, if you'are using a FPGA family that has dynamical phase align features or if you have to achieve phase alignment manually.