Honored ContributorThe codes here:
always @(posedge clk or negedge rst)begin if(!rst)begin ..... end else begin if(a) .... if(b) .... if(c) .... end end I found that the synthesised circuit is priority,i.e.there are selectors.But I want them to be parallel!How can I do with that? Please! (the synthesis attributes like "synthesis parallel_case","synthesis full_case" are adapt to the "cae"sentence,not "if" sentence.)
Honored ContributorLooking at your code, the rst and clk signal tests have a priority relation due to the else. This implements asynchronously resetable flip-flops.
Unless the if(b) is not in an else path of if(a), there should be no priority of the if's, but there may be priority with your assigned signals - for example, if you set signal x = 1 in the if(a) part and x = 2 in the if(b) part and both a and b are true, x will be 2 after the rising clk edge even though it has been set to 1 in the if(a) part... which has been overridden by the if(b) part in such a case. Hope that helps...Honored Contributor
