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allen18's avatar
allen18
Icon for Occasional Contributor rankOccasional Contributor
3 years ago
Solved

How to synchronize the inputs of multiple ADC chips using the JESD204B IP core in an FPGA?

Hello everyone, I have encountered some issues in designing an FPGA solution for receiving ADC data. The FPGA I am using is stratix10-1SX110HN2F43I2VG, which has two tiles, with each tile hav...
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  • allen18's avatar
    allen18
    3 years ago

    I have solved this problem. I used a clock buffer chip to replicate multiple sets of clocks.

ZH_Intel's avatar
ZH_Intel
Icon for Frequent Contributor rankFrequent Contributor
3 years ago

Hi Allen,

Apologize for the delayed response as we encounter some technical difficulty.

Glad that your problem is solved, I now transition this thread to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread.


Thank you.

Best Regards,

ZulsyafiqH_Intel