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allen18
Occasional Contributor
Occasional ContributorHow to synchronize the inputs of multiple ADC chips using the JESD204B IP core in an FPGA?
Hello everyone, I have encountered some issues in designing an FPGA solution for receiving ADC data. The FPGA I am using is stratix10-1SX110HN2F43I2VG, which has two tiles, with each tile hav...
I have solved this problem. I used a clock buffer chip to replicate multiple sets of clocks.
allen18Occasional Contributor
Occasional ContributorI have solved this problem. I used a clock buffer chip to replicate multiple sets of clocks.
