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Altera_Forum
Honored Contributor
11 years agoUsually, for a state machine, you would make the state a signal rather than variable, as well as leaving it as an enumerated type.
is there what you expect in the RTL diagram?Usually, for a state machine, you would make the state a signal rather than variable, as well as leaving it as an enumerated type.
is there what you expect in the RTL diagram?