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MPM00's avatar
MPM00
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6 years ago

How to solve error while generating HDL? Altera DE2 -115 based video processing project

Hi, https://www.youtube.com/watch?v=etUWT-H3mYM I m trying to do the design specified in the video tutorial(link above). And i managed to connect all blocks without error. but while generating hd...
AnandRaj_S_Intel's avatar
AnandRaj_S_Intel
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6 years ago

Hi Mebin,

Please share the project let me check.

MPM00's avatar
MPM00
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6 years ago

HI,

Thanks for the quick reply.

My project file attached in the link.

https://drive.google.com/open?id=1Y5eHiukBCOFPz1mRIveyqjRW2bj-8aYV

Sir i cleared the errors while generating the HDL bu changing data bits per symbol and plane. I don't know whether it will work on the DE-2 board.

I m doing this for my set project.(I m from VIT vellore,Mtech VLSI Design).

Our project is face recognition. We are using two algorithms in this project. One is face detection algorithm- Viola Jones and second one is face recognition algorithm -Principal component analysis.

I don't how to implement these algorithms in FPGA. We have no option to use NIOS. Can you please help me to how it can be done?

We are confused to how to insert this implemented algorithms into this design.

We are just beginners. We are using verilog HDL

Regards,

Mebin