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the .vo file is one of the output file when I press the "Generate", the problem is it is encrypted and not recognized by ncsim.
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I did generate a sample NIOS II system using QII 17.1 with DMA, on-chip SSRAM, FIR Module, etc. The output directory has a simulation folder, which has the simulation libraries for all the system components and there is a "submodules" folder which contains all the Verilog models of the modules. These are .v files and not .vo .
All of the Altera system IPs will be encrypted, but that does not mean the Sim tools cannot read them. Sim tools are capable of reading in encrypted RTL files and can use them in simulations. I have simulated various designs with 3rd party encrypted cores and it works properly. Did you look for the Generate simulation models option and enable it?
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