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Sijith's avatar
Sijith
Icon for Occasional Contributor rankOccasional Contributor
3 years ago
Solved

How to simulate a design created in Platform Designer System

As I am comparatively new to Quartus Prime, I would like to know how to simulate my design that is created using Platform Designer System. I would like to elaborate a bit: my counter.v module is co...
  • ShengN_altera's avatar
    ShengN_altera
    3 years ago

    Hi,

    The testbench counter_fifo_tb.v that I sent to you before is just an example. If you want to get proper output waveform, you have to change a bit on the stimulus.

    Below attached the edited testbench and proper output waveform image. As for the functionality, probably you still need to further verify from your side.

    Thanks,

    Best Regards,

    Sheng

ShengN_altera's avatar
ShengN_altera
Icon for Super Contributor rankSuper Contributor
3 years ago

Hi,

Check the design zip file qwork1.zip attached and document inside the zip file. Check also this link https://www.intel.com/content/www/us/en/support/programmable/support-resources/design-examples/horizontal/exm-avalon-verification-ip.html for example design and pdf. Probably you'll have better understanding on BFM and test program. The test program is similar and applicable to the question 3) you wrote. `define MSTR_BFM mstr_test_prog.mstr_bfm_top.mastr_bfm this define the Master BFM id in platform designer. The set_command_<X> (Y) you can find in the pdf.

For IP's + VHDL module, you have to instantiate the IP's top module (in your case counter_fifo_inst.vhd) in VHDL module in order to connect them. Then the combined simulation setup script is needed like this video link posted before.

Thanks,

Best Regards,

Sheng

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