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Sijith's avatar
Sijith
Icon for Occasional Contributor rankOccasional Contributor
3 years ago
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How to simulate a design created in Platform Designer System

As I am comparatively new to Quartus Prime, I would like to know how to simulate my design that is created using Platform Designer System. I would like to elaborate a bit: my counter.v module is co...
  • ShengN_altera's avatar
    ShengN_altera
    3 years ago

    Hi,

    The testbench counter_fifo_tb.v that I sent to you before is just an example. If you want to get proper output waveform, you have to change a bit on the stimulus.

    Below attached the edited testbench and proper output waveform image. As for the functionality, probably you still need to further verify from your side.

    Thanks,

    Best Regards,

    Sheng

Sijith's avatar
Sijith
Icon for Occasional Contributor rankOccasional Contributor
3 years ago

Thank you very much and much appreciated your help.

I have a question, as a contributor mentioned about the use of BFM : https://cdrdv2.intel.com/v1/dl/getContent/653122?explicitVersion=true to simulate the Platform Designer generated design. If that is also a recommended solution, could you please address the question I wrote on 05-23-2023 (please click on this date for the link to message).

I have a completely different question too in one of your comment you said "Since your design only involved IP". I am afraid that I did not get it well. Is there any possible other scenario like, designs with IP's + VHDL module component (not converting to custom IP) in a project? If so how can they get connected in a project. I assume that the Platform Designer only supports connecting between IP's (off the shelf or custom built)?

Thanks again.

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